1. Technical Field
The embodiments described herein relate to a semiconductor integrated circuit, and more particularly, to an input circuit of a semiconductor integrated circuit.
2. Related Art
Generally, in a semiconductor integrated circuit (e.g., a semiconductor memory apparatus) a signal that is input from outside the semiconductor memory apparatus is first applied to an input buffer block where it is buffered at a voltage level that is used in the semiconductor memory apparatus.
As shown in FIG. 1, a conventional input buffer block 100 can be configured to be activated/deactivated by an enable signal “ENABLE.” The input buffer block 100 can be configured to receive a clock signal “CLK” as a first input signal and a clock bar signal “CLKB” as a second input signal, buffer the first and second input signals, and generate an output signal “CKOUT.”
That is, when a voltage level of the clock signal “CLK” is higher than that of the clock bar signal “CLKB,” a second NMOS transistor N2 can be turned off, and a first NMOS transistor (N1) can be turned on. Thus, the output signal “CKOUT” has a voltage level at a “high” level. Meanwhile, when a voltage level of the clock bar signal “CLKB” is higher than that of the clock signal “CLK,” the first NMOS transistor (N1) can be turned off, the second NMOS transistor (N2) can be turned on, and the first PMOS transistor (P1) and the second PMOS transistor (P2) can both be turned on. If the first PMOS transistor (P1) is turned on, the output signal “CKOUT” becomes a voltage level at a “low” level.
FIG. 2 is a timing diagram illustrating a waveform of an input buffer block shown in FIG. 1. Referring to FIG. 2, generally, an average voltage level of the pair of input signals “CLK” and “CLKB” whose phases are opposite to each other, must be the same as a cross voltage (Vcross) of the input signals “CLK” and “CLKB.”
Assuming that a cross voltage (Vcross) required in a data sheet is a reference voltage (Vref), then when a voltage level of the cross voltage (Vcross) is the same as a voltage level of the reference voltage (Vref), the input buffer block can have a normal output signal “CKOUT” that has a constant delay time.
FIG. 3 is a timing diagram illustrating an output signal “CKOUT” when a cross voltage (Vcross) of a clock signal “CLK” and a clock bar signal “CLKB” is higher than a reference voltage (Vref).
In general, the input buffer block 100 is typically configured to operate when a signal having the same cross voltage (Vcross) as the reference voltage (Vref) is input. However, as shown in FIG. 3, when the cross voltage (Vcross) is higher than the reference voltage (Vref), a voltage level at a first node (Nd1) of FIG. 1 can become lower than a normal voltage level of a “low/high” level.
For example, if a phase of the clock signal “CLK” is inverted from “high” to “low” and a phase of the clock bar signal “CLKB” is inverted from “low” to “high”, the voltage level at the first node (Nd1) can be inverted from the “low” level to the “high” level. However, since the first node (Nd1) has a voltage level lower than a normal low level, an inversion time can be extended. At that time, the inversion time becomes a delay time. For this reason, a falling time of the output signal “CKOUT” can be delayed.